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free CLKM clock rate change. Otherwise (CLKM_SHA_SEL = 1) the new clock rate is
supplied when leaving the SLEEP state the next time.
To reduce power consumption and spurious emissions, it is recommended to turn off
the Atmel AT86RF232 CLKM clock when not in use.
Note:
1. During reset procedure, see Section 7.1.2.7 , register bits CLKM_CTRL
are shadowed. Although the clock setting of CLKM remains after reset,
a read access to register bits CLKM_CTRL delivers the reset value one.
For that reason it is recommended to write the previous configuration
(before reset) to register bits CLKM_CTRL to align the radio transceiver
behavior and register configuration. Otherwise the CLKM clock rate is
set back to the reset value (1MHz) after the next SLEEP cycle.
9.6.5 Register Description
Register 0x03 (TRX_CTRL_0):
The TRX_CTRL_0 register controls the CLKM clock rate.
Figure 9-13 . Register TRX_CTRL_0.
Bit
0x03
Read/Write
Reset value
Bit
0x03
Read/Write
Reset value
7
R/W
0
3
CLKM_SHA_SEL
R/W
1
6
R
0
2
R/W
0
reserved
5
R/W
0
1
CLKM_CTRL
R/W
0
4
R/W
0
0
R/W
1
TRX_CTRL_0
TRX_CTRL_0
? Bit 3 - CLKM_SHA_SEL
The register bit CLKM_SHA_SEL defines if a new clock rate, defined by CLKM_CTRL,
is set immediately or after the next SLEEP cycle.
Table 9-12. CLKM_SHA_SEL.
Register Bits
CLKM_SHA_SEL
Value
0
1
Description
CLKM clock rate change appears immediately
CLKM clock rate change appears after SLEEP cycle
? Bit 2:0 - CLKM_CTRL
The register bits CLKM_CTRL sets the clock rate of pin 17 (CLKM).
Table 9-13. CLKM_CTRL.
116
AT86RF232
Register Bits
CLKM_CTRL
Value
0
1
7
Description
No clock at pin CLKM, pin set to logic low
1MHz
62.5kHz (IEEE 802.15.4 symbol rate)
All other values are reserved
8321A – MCU Wireless – 10/11
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